1. Field of the Invention
The present invention relates to an oscillator, a PLL circuit, communication equipment, and an oscillating method.
2. Related Art of the Invention
Voltage-controlled oscillators are widely used as means of generating local oscillation signals for wireless communication equipment (for example, see Japanese Patent Laid-Open No. 2000-224027). FIG. 9 shows an example of a configuration of a conventional voltage-controlled oscillator. In this figure, the voltage-controlled oscillator is composed of coils 101 and 102, capacitors 103 and 106, a variable capacitor (varactor) 105, oscillation transistors 107 and 108, a current source 116, a power terminal 110, and a voltage control terminal 111. In this figure, a bias circuit and the like are omitted.
With reference to FIG. 9, description will be given below of operations of a conventional voltage-controlled oscillator. A parallel resonance circuit is composed of the coils 101 and 102, the capacitor 103, and the varactor 105. In this case, the capacitance of the varactor 105 is determined by a differential voltage between a control voltage applied to the voltage control terminal 111 and a supply voltage. This in turn determines a resonance frequency for the resonance circuit. The oscillation transistors 107 and 108 generate a negative resistance to cancel losses caused by a parasitic resistance component of the resonance circuit. Thus, in the voltage-controlled oscillator shown in FIG. 9, the control voltage (control signal) can be used to vary an oscillation frequency.
However, such a voltage-controlled oscillator creates the following problems: (1) If noise is superimposed on a voltage control line (i.e. a line leading to the voltage control terminal), the voltage across the varactor 105 may change to change the oscillation frequency. (2) If noise is superimposed on a supply line (a line leading to the power terminal 110), the voltage across the varactor 105 may also change to change the oscillation frequency. Further, the varactor 105 has different parasitic capacitance to ground at each nodes owing to its structure. (3) Such a difference in parasitic capacitance to ground may adversely affect the resonance circuit.
In order to solve the problems (1) and (2), a capacitor 104 has been inserted between the varactor 105 and the coil 101 to hinder a power voltage as shown in FIG. 10. A control signal is thus inputted to the opposite ends of the varactor 105 via voltage control terminals 112 and 113. With this arrangement, even if noise is superimposed on the control signal, a differential voltage between the signals from the voltage control terminals 112 and 113 is applied across the varactor 105. Consequently, the noise component is canceled. Further, the power voltage is not applied across the varactor 105. Even if noise passing through the capacitors 104 and 103 is superimposed on the supply line, voltages having the same magnitude of the noise component are applied to the respective ends of the varactor 105. This serves to avoid the adverse effects of noise on the supply line.
Further, in order to solve the above problem (3), a voltage-controlled oscillator may be used in which as shown in FIG. 11, a varactor 119 arranged oppositely with respect to the varactor 105 and having the same characteristics as those of the varactor 105 is installed in place of the capacitor 103 shown in FIG. 9. In the voltage-controlled oscillator configured as described above, the varactors 105 and 119 cooperate in balancing the parasitic capacitance to ground in the circuit as a whole. This avoids affecting adversely the resonance circuit.
However, the circuit shown in FIG. 11 cannot solve the above problems (1) and (2). Accordingly, in view of this, the circuit shown in FIG. 12 may be used. In addition to the series circuit composed of the varactors 105 and 119 as shown in FIG. 11, the circuit shown in FIG. 12 has a series circuit composed of varactors 114 and 115 connected in series oppositely with respect to those of the varactors 105 and 119, respectively, this second series circuit being connected in parallel with the first series circuit. Further, a voltage control terminal 113 is connected between the varactors 105 and 119, while a voltage control terminal 112 is connected between the varactors 114 and 115. This circuit can solve the above problems (1) and (2) while balancing the parasitic capacitance to ground in the circuit as a whole.
However, the circuit shown in FIG. 10 can solve the problems (1) and (2) but not the problem (3).
Further, with the circuit shown in FIG. 12, no problems occur if each varactor has a linear voltage-capacitance characteristic. However, if this characteristic is nonlinear, the circuit in FIG. 12 cannot solve the problem (1) or (2). This will be described with reference to FIG. 13.
FIG. 13 shows a part composed of the varactors 105, 119, 114, and 115 from FIG. 12. First, an initial state is assumed in which a voltage of 2 V is applied to the voltage control terminal 112, a voltage of 4 V is applied to the voltage control terminal 113, and a voltage of 3 V is applied to the supply line. In this case, a voltage of 1 V, i.e. a difference between the voltage of each voltage control terminal and the supply voltage, is applied across each varactor. When a capacitance determined by each varactor is defined as C, the capacitance of the whole circuit, shown in FIG. 13, is expressed as follows:(C×C)/(C+C)+(C×C)/(C+C)=C  [Equation 1]
Now, it is assumed that noise is superimposed on the voltage control line. Since each voltage control line is expected to be equally affected by noise, a noise component of the same phase is superimposed on each voltage control line. That is, it is assumed that a noise component of 0.1 V affects the voltage applied to the voltage control terminal 112, i.e. 2 V, which thus becomes 2.1 V. It is similarly assumed that a noise component of 0.1 V affects the voltage applied to the voltage control terminal 113, i.e. 4 V, which thus becomes 4.1 V.
In this case, the voltage applied to the varactors 114 and 115 is 3−2.1=0.9 V. The voltage applied to the varactors 105 and 119 is 4.1−3=1.1 V. Here, if each varactor is assumed to have linear characteristics, the varactors 114 and 115 have a capacitance of 0.9 C, whereas the varactors 105 and 119 have a capacitance of 1.1 C. As described above, the capacitance of the whole circuit, shown in FIG. 13, is calculated as follows:(0.9C×0.9C)/(0.9C+0.9C)+(1.1C×1.1C)/(1.1C+1.1C)=C  [Equation 2]
However, each varactor generally has a nonlinear voltage-capacitance characteristic, for example, as shown in FIG. 14. With such non-linearity assumed, for example, the varactors 114 and 115 have a capacitance of 3 C, whereas the varactors 105 and 119 have a capacitance of 0.5 C. In this case, the capacitance of the whole circuit, shown in FIG. 13, is calculated as follows:(0.5C×0.5C)/(0.5C+0.5C)+(3C×3C)/(3C+3C)=1.75C  [Equation 3]This deviates from the result obtained under the assumption that each varactor has linear characteristics. As described above, with the non-linearity of each varactor assumed, the circuit shown in FIG. 12 cannot solve the above problem (1).
Further, FIG. 21 shows a variation (see U.S. Pat. No. 6,292,065) of the circuit shown in FIG. 12. In the circuit shown in FIG. 21, a bias voltage is applied to terminals 162, 164, 166, and 168. A signal voltage is inputted to terminals 1118 and 1120. If varactors 122, 124, 126, and 128 have nonlinear characteristics, this circuit also cannot solve the problem (1) for a reason similar to that described above.